1. Field of the Invention
The present invention relates to a fully integrated, CMOS voltage multiplier particularly useful for EPROM and EEPROM memory devices.
2. Description of the Prior Art
In consideration of the fact that wholly integrated voltage multipliers are capable of generating a relatively high voltage, obtained by multiplying a relatively low supply voltage, suiting the level required when writing and erasing CMOS-EEPROM memories through the Fowler-Nordheim tunnelling mechanism, the practice of integrating voltage multipliers in such memory devices for this purpose has become very common. In other integrated circuits it may also be useful to integrate a voltage multiplier as for example in EPROM memories for the purpose of rising the gate voltage of the input transistor of the high voltage supply of the circuitry in order not to subtract such a high voltage from the transistor's threshold.
The voltage multiplier is a well known circuit and a diagram thereof is depicted in FIG. 1. Phi 1 and phi 2 are two square-wave signals, substantially in phase opposition between themselves, generated by a suitable oscillator. By supposing ideal the diodes and the square-wave signals to have an amplitude equal to the supply voltage Vcc, the asymptotic level approached by the output voltage Vout, in an open circuit situation, is equal to n times Vcc, wherein n is the number of stages of the multiplier circuit. In a starting condition with all the capacitors discharged and phi 1=Vcc and phi 2=0, the C1 capacitor charges to the Vcc voltage, while the capacitor C2 is still uncharged. When phi 1 and phi 2 switch, because the diode cannot sustain a positive voltage across its terminals, the capacitor C1 pours charge in the capacitor C2, which thus charges to the voltage Vcc; a similar transfer of electrical charge will occur from all odd numbered capacitors to the even numbered capacitors in the diagram of FIG. 1. When phi 1 and phi 2 switch again, the capacitor C1 recharges through the supply and no return of charge from C2 occurs because the diode D1 is reverse biased; similarly all the other odd numbered capacitors recharge by means of the current provided by the preceding stage (to the left thereof in the diagram). Under open circuit conditions, i.e., when no current is drawn from the output terminal of the last stage, the Vout will be decisively greater than Vcc because of the transfer of electrical charge from the preceding stage; moreover, the current drawn from the preceding stage upon any subsequent switching will become progressively smaller because the output capacitor will result already partially charged. At steady state, any intermediate node of the voltage multiplier assumes a voltage greater than the preceding intermediate node by a quantity equal to the supply voltage, and therefore the output voltage Vout is equal to n times the supply voltage Vcc. The theoretical value of n.multidot.Vcc represents an upper limit which cannot be reached in practice. Deviations from such an ideal condition being due to the following reasons:
(a) a diode has a threshold voltage Vt&gt;0 and therefore not all the electrical charge C.multidot.Vcc may be transferred to the following stages as in an ideal situation, and therefore any diode is in practice biased at a voltage equal to Vcc-Vt. Moreover a diode has an intrinsic ON resistance which causes a further voltage drop thereacross during the conduction phase of the diode;
(b) the switching signals phi 1 and phi 2 are not ideal square-waves and do not ensure a Vcc voltage for the entire cycle of electrical charge transfer from a stage to a following stage;
(c) the circuit components of an integrated voltage multiplier have parasitic capacitances toward the substrate and the effect of these capacitances is that of limiting the charge transfer to the multiplier because a portion of the electrical charge flows directly to the substrate;
(d) the current drawn from the output terminal of the multiplier is not negligeable and therefore the output Ro resistance of the multiplier circuit affects the ultimate output voltage which may be practically reached. Said output resistance Ro may be easily calculated through a simplified analysis of the multiplier circuit. The (maximum) amount of charge transferred in a cycle equals to: C.multidot.Vcc, so that, being T the period of the oscillator which generates the two phases phi 1 and phi 2, it is ##EQU1## where f=1/T is the frequency of the oscillator, Therefore the output resistance is given by: ##EQU2##
In order to decrease Ro it is therefore necessary to increase C and the frequency of the oscillator. A practical upper limit for this frequency is in the order of about 10 MHz. Typical capacitance values which may be integrated without an excessive area requirement are of about few pF. It follows that a typical value of Ro is of about 100K ohm per stage. This non-negligeable output resistance vanifies efforts to increase the output voltage by increasing the number of stages beyond a certain limit because the concomitant increase of the total output resistance Ro reduces the current which may be delivered to the high voltage rail. In the publication "IEEE Transaction of Electron Devices" VOL.ED-27, NO. 7, July 1980, Pages 1211-1216, a 1.5 V supply voltage embodiment of an integrated multiplier utilizing bipolar diodes obtained by flanking a p-doped polysilicon to an n-doped polysilicon is described. Such a solution obviously requires additional masks, and furthermore the threshold of those diodes has a large spread. The most commonly used form of this circuit, both in NMOS and in CMOS technology, contemplates the use of n-channel MOS transistors with gate and drain connection in common in place of bipolar diodes, as shown in FIG. 2. If the ratio W/L (Width/Length) of each transistor is sufficiently large in respect to the current flowing therethrough, the Vgs voltage will always be slightly higher than the threshold and the behaviour of the transistor will approximate that of a diode having a threshold similar to the threshold of a MOS transistor. It is not convenient to excessively increase the width (W) of the transistor in order to avoid that the parasitic capacitances toward the substrate (which are approximatively proportional to W.multidot.L) become comparable to the capacitances of the multiplier circuit.
There is however a substantial difference between a diode made by means of a MOS transistor and a true bipolar diode. The latter has a threshold voltage of about 0.6 V, which would be constant for all the stages of the multiplier circuit, while the threshold voltage of a MOS transistor increases because of the "body" effect whenever the source voltage Vs departs from the value of the body voltage Vb in accordance with the known law: ##EQU3## where Vto is the threshold voltage when the voltage difference between source and body (Vsb) is equal to zero and where .PHI.F is the electrostatic potential of the p-type substrate at equilibrium and .gamma. is an empirically evaluated constant depending on the specific fabrication process used. For typical values of .gamma. (0.47) and of Vto (900 mV) for n-channel transistors, the transistor threshold in the last stages of the multiplier circuit, wherein the source voltage rises beyond 15 V, is higher than 2.3 V. Even by utilizing nonimplanted transistors having, for example, a 600 mV lower threshold voltage and a .gamma. slightly reduced, the threshold remains higher than 1.5 V, i.e. much higher than that of bipolar diodes. This disadvantage, which may be acceptable with a 5 V supply, becomes highly penalizing when the supply (and therefore the amplitude of the square-wave signals fed to the circuit) drops below 3 V, so that more than 50% of this voltage is lost across the MOS diodes and the voltage multiplier's efficiency drops dramatically. In this case the voltage increment from one stage to the following is very small and the number of stages required to reach e.g. 18-20 V would result in an extremely high Ro. A susbtantial improvement could be achieved by utilizing a depletion-type transistor for the last stages with a negative threshold such as to nullify the body effect. The average threshold of the MOS diodes would then approach that of bipolar diodes. For fabricating a depletion transistor additional masks and process steps are needed, with an attendant increase of the fabrication costs and therefore alternative means for obviating to the problem are sought.